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IA4421 Universal ISM Band FSK Transceiver
DESCRIPTION
Integration's IA4421 is a single chip, low power, multi-channel FSK transceiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 433, 868 and 915 MHz bands. The IA4421 transceiver is a part of Integration's EZRadioTM product line, which produces a flexible, low cost, and highly integrated solution that does not require production alignments. The chip is a complete analog RF and baseband transceiver including a multi-band PLL synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation. The IA4421 features a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLL's high resolution allows the usage of multiple channels in any of the bands. The receiver baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and crystal tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation. Consequently, no external components (except crystal and decoupling) are needed in most applications. The IA4421 dramatically reduces the load on the microcontroller with the integrated digital data processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost) crystal. To minimize the system cost, the IA4421 can provide a clock signal for the microcontroller, avoiding the need for two crystals. For low power applications, the IA4421 supports low duty cycle operation based on the internal wake-up timer.
IA4421
PIN ASSIGNMENT
See back page for ordering information.
FEATURES
* * * * * * * * * * * * * * * * * * * * * * * * * * * * Fully integrated (low BOM, easy design-in) No alignment required in production Fast-settling, programmable, high-resolution PLL synthesizer Fast frequency-hopping capability High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode) Direct differential antenna input/output Integrated power amplifier Programmable TX frequency deviation (15 to 240 kHz) Programmable RX baseband bandwidth (67 to 400 kHz) Analog and digital RSSI outputs Automatic frequency control (AFC) Data quality detection (DQD) Internal data filtering and clock recovery RX synchron pattern recognition SPI compatible serial control interface Clock and reset signals for microcontroller 16 bit RX Data FIFO Two 8 bit TX data registers Low power duty cycle mode Standard 10 MHz crystal reference with in circuit calibration Wake-up timer 2.2 to 3.8 V supply voltage Low power consumption Low standby current (0.3 A) Compact 16 pin TSSOP package Supports very short packets (down to 3 bytes) High quality temperature stability of the RF parameters High quality adjacent channel rejection/blocking
FUNCTIONAL BLOCK DIAGRAM
MIX I AMP OC clk LNA RF2 12 MIX Q Self cal. I/Q DEMOD Data Filt CLK Rec data 6 7 DCLK / CFIL / FFIT / FSK / DATA / nFFS
RF1 13
AMP
OC FIFO
PA
PLL & I/Q VCO with cal. RF Parts BB Amp/Filt./Limiter
RSSI
COMP
DQD
AFC Data processing units
TYPICAL APPLICATIONS
* * * * * * * * * Home security and alarm Remote control, keyless entry Wireless keyboard/mouse and other PC peripherals Toy controls Remote keyless entry Tire pressure monitoring Telemetry Personal/patient data logging Remote automatic meter reading 1
CLK div
Xosc
WTM with cal.
LBD Low Power parts
Controller
Bias
8 CLK
9 XTL / REF
15 ARSSI
1 SDI
2 SCK
3
4
5 nIRQ
10 nRES
16 nINT / VDI
11 VSS
14 VDD
nSEL SDO
IA4421-DS rev 2.1r 0207
PRELIMINARY
www.integration.com
IA4421 DETAILED FEATURE-LEVEL DESCRIPTION
The IA4421 FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application. The IA4421 incorporates a fully integrated multi-band PLL synthesizer, PA with antenna tuning, an LNA with switchable gain, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter.
PLL
The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL's high resolution allows the usage of multiple channels in any of the bands.
Data Filtering and Clock Recovery
Output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate. The FIFO can not be used in this mode and clock is not provided for the demodulated data. Digital operation: A digital filter is used with a clock frequency at 29 times the bit rate. In this mode there is a clock recovery circuit (CR), which can provide synchronized clock to the data. Using this clock the received data can fill a FIFO. The CR has three operation modes: fast, slow, and automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate data timing than in fast mode. In automatic mode the CR automatically changes between fast and slow mode. The CR starts in fast mode, then after locking it automatically switches to slow mode (Only the digital data filter and the clock recovery use the bit rate clock. For analog operation, there is no need for setting the correct bit rate.)
RF Power Amplifier (PA)
The power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called "hand effect".
LNA
The LNA has approximately 250 Ohm input impedance, which functions well with the proposed antennas (see: Application Notes available from www.integration.com) If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide the correct matching and to minimize the noise figure of the receiver. The LNA gain can be selected in four steps (between 0 and -20dB relative to the highest gain) according to RF signal strength. It can be useful in an environment with strong interferers.
Baseband Filters
The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver according to the characteristics of the signal to be received. An appropriate bandwidth can be chosen to accommodate various FSK deviation, data rate and crystal tolerance requirements. The filter structure is 7th order Butterworth low-pass with 40 dB suppression at 2*BW frequency. Offset cancellation is done by using a high-pass filter with a cut-off frequency below 7 kHz.
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IA4421
Data Validity Blocks
RSSI
A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on the external filter capacitor. Pin 15 is used as analog RSSI output. The digital RSSI can be monitored by reading the status register. When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Configuration Setting Command, the chip provides a fixed number (196) of further clock pulses ("clock tail") for the microcontroller to let it go to idle or sleep mode. If this clock output is not used, turn the output buffer off by the Power Management Command.
Low Battery Voltage Detector
The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. The detector circuit has 50 mV hysteresis.
Analog RSSI Voltage vs. RF Input Power
Wake-Up Timer
The wake-up timer has very low current consumption (1.5 uA typical) and can be programmed from 1 ms to several days with an accuracy of 10%. The wake-up timer calibrates itself to the crystal oscillator at every startup. For proper calibration of the wake-up timer the crystal oscillator must be running before the wake-up timer is enabled. The calibration process takes approximately 0.5ms. For the crystal start up time (tsx), see page 10.
Event Handling
P1 P2 P3 P4 -65 dBm -65 dBm -100 dBm -100 dBm 1300 mV 1000 mV 600 mV 300 mV
DQD
The operation of the Data Quality Detector is based on counting the spikes on the unfiltered received data. High output signal indicates an operating FSK transmitter within baseband filter bandwidth from the local oscillator. DQD threshold parameter can be set by using the Data Filter Command.
In order to minimize current consumption, the transceiver supports different power saving modes. Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the serial interface). If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The source of the interrupt can be read out from the transceiver by the microcontroller through the SDO pin.
AFC
By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the TX/RX offset in discrete steps, allowing the use of:
Interface and Controller
An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock, wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the transceiver and the received data. The transmitter block is equipped with two 8 bit wide TX data registers. It is possible to write 8 bits into the register in burst mode and the internal bit rate generator transmits the bits out with the predefined rate. For further details, see the TX Register Buffered Data Transmission section. It is also possible to store the received data bits into a FIFO register and read them out in a buffered mode.
* Narrower receiver bandwidth (i.e. increased sensitivity) * Higher data rate * Inexpensive crystals
Crystal Oscillator
The IA4421 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The transceiver can supply a clock signal for the microcontroller; so accurate timing is possible without the need for a second crystal.
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IA4421
PACKAGE PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
Pin 1 2 3 4 5
Name SDI SCK nSEL SDO nIRQ FSK DATA nFFS DLCK
Type DI DI DI DO DO DI DO DI DO AIO DO DO AIO AIO DIO S AIO AIO S AO DI DO
Function Data input of the serial control interface (SPI compatible) Clock input of the serial control interface Chip select input of the serial control interface (active low) Serial data output with bus hold Interrupt request output (active low) Transmit FSK data input (internal pull up resistor 133 k) Received data output (FIFO not used) FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration Setting Command (internal pull up resistor 133 k) Received data clock output (Digital filter used, FIFO not used) External data filter capacitor connection (Analog filter used) FIFO interrupt (active high) Number of the bits in the RX FIFO has reached the preprogrammed limit In FIFO mode, when bit ef is set in Configuration Setting Command Microcontroller clock output Crystal connection (the other terminal of crystal to VSS) or external reference input External reference input. Use 33 pF series coupling capacitor Open drain reset output with internal pull-up and input buffer (active low) Ground reference voltage RF differential signal input/output RF differential signal input/output Positive supply voltage Analog RSSI output Interrupt input (active low) Valid data indicator output
6
7
CFIL FFIT
8 9 10 11 12 13 14 15 16
CLK XTL REF nRES VSS RF2 RF1 VDD ARSSI nINT VDI
Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver.
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IA4421
PIN6 Internal Structure (FSK / DATA / nFFS)
PIN10 Internal Structure (nRES I/O)
* Note: These pins can be left floating.
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PRELIMINARY
IA4421
Typical Application
Typical application with FIFO usage
Mode el=0 in Configuration Setting Command Transmit el=1 in Configuration Setting Command
Microcontroller
Pin 6 TX Data input nFFS input (TX Data register can be accessed) RX Data output nFFS input ef=1 in Configuration Setting Command (RX Data FIFO can be accessed)
Pin 7
Not used
ef=0 in Configuration Setting Command Receive
RX Data clock output
FFIT output
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PRELIMINARY
IA4421 GENERAL DEVICE SPECIFICATIONS
All voltages are referenced to Vss, the potential on the ground reference pin VSS.
Absolute Maximum Ratings (non-operating)
Symbol Vdd Vin Voc Iin ESD Tst Tld Parameter Positive supply voltage Voltage on any pin (except RF1 and RF2) Voltage on open collector outputs (RF1, RF2) Input current into any pin except VDD and VSS Electrostatic discharge with human body model Storage temperature Lead temperature (soldering, max 10 s) -55 Min -0.5 -0.5 -0.5 -25 Max 6 Vdd+0.5 Vdd+1.5 (Note 1) 25 1000 125 260 Units V V V mA V
o o
C C
Recommended Operating Range
Symbol Vdd Voc Top Parameter Positive supply voltage Voltage range on open collector outputs (RF1, RF2) Ambient operating temperature Min 2.2 Vdd-1.5 (Note 2) -40 Max 3.8 Vdd+1.5 85 Units V V
o
C
Note 1: Cannot be higher than 7 V. Note 2: Cannot be lower than 1.2 V.
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PRELIMINARY
IA4421 ELECTRICAL SPECIFICATION
Test Conditions: Top = 27 oC; Vdd = Voc = 3.3 V)
DC Characteristics
Symbol Idd_TX_0 Parameter Supply current (TX mode, Pout = 0 dBm) Conditions/Notes 433 MHz band 868 MHz band 915 MHz band Idd_TX_PMAX Supply current (TX mode, Pout = Pmax) 433 MHz band 868 MHz band 915 MHz band 433 MHz band Idd_RX Ipd Ilb Iwt Ix Vlb Vlba Vil Vih Iil Iih Vol Voh Supply current (RX mode) Standby current (Sleep mode) Low battery voltage detector current consumption Wake-up timer current consumption Idle current Low battery detect threshold Low battery detection accuracy Digital input low level voltage Digital input high level voltage Digital input current Digital input current Digital output low level Digital output high level Vil = 0 V Vih = Vdd, Vdd = 3.8 V Iol = 2 mA Ioh = -2 mA Vdd-0.4 0.7*Vdd -1 -1 1 1 0.4 Crystal oscillator on (Note 1) Programmable in 0.1 V steps 2.25 +/- 3 0.3*Vdd 868 MHz band 915 MHz band All blocks disabled Min Typ 15 16 17 22 23 24 11 12 13 0.3 0.5 1.5 0.6 26 27 28 13 14 15 1 1.7 3.5 1.2 3.75 A A A mA V % V V A A V V mA mA mA Max Units
Notes are on page 11.
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IA4421
AC Characteristics (PLL parameters)
Symbol fref Parameter PLL reference frequency Receiver LO/Transmitter carrier frequency Conditions/Notes (Note 2) 433 MHz band, 2.5 kHz resolution fo 868 MHz band, 5.0 kHz resolution 915 MHz band, 7.5 kHz resolution tlock tst, P PLL lock time PLL startup time (Note 10) Frequency error < 1kHz after 10 MHz step With a running crystal oscillator Min 9 430.24 860.48 900.72 30 200 300 Typ 10 Max 11 439.75 879.51 929.27 us us MHz Units MHz
AC Characteristics (Receiver)
Symbol Parameter Conditions/Notes mode 0 mode 1 BW Receiver bandwidth mode 2 mode 3 mode 4 mode 5 BRRX BRARX Pmin AFCrange IIP3inh IIP3outh IIP3inl IIP3outl Pmax Cin RSa RSr RSps CARSSI RSstep RSresp Psp_rx FSK bit rate (Note 10) FSK bit rate (Note 10) Receiver Sensitivity AFC locking range Input IP3 Input IP3 IIP3 (LNA -6 dB gain) IIP3 (LNA -6 dB gain) Maximum input power RF input capacitance RSSI accuracy RSSI range RSSI power supply dependency Filter capacitor for ARSSI RSSI programmable level steps DRSSI response time Receiver spurious emission Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit CARRSI = 4.7 nF When input signal level lower than -54 dBm and greater than -100 dBm 1 6 500 -60 With internal digital filters With analog filter BER 10 , BW=67 kHz, BR=1.2 kbps, 868 MHz Band (Note 3) dfFSK: FSK deviation in the received signal In band interferers in high bands (868 MHz, 915 MHz) Out of band interferers l f-fo l > 4 MHz In band interferers in low band (433 MHz) Out of band interferers l f-fo l > 4 MHz LNA: high gain 0 1 +/- 6 46 +35
-3
Min
Typ 67 134 200 270 340 400
Max
Units
kHz
0.6
115.2 256 -110 0.8*dfFSK -21 -18 -15 -12
kbps kbps dBm
dBm dBm dBm dBm dBm pF dB dB mV/V nF dB us dBm
Notes are on page 11.
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IA4421
AC Characteristics (Transmitter)
Symbol IOUT Pmax_50 Parameter Open collector output DC current Max. output power delivered to 50 Ohm load over a suitable matching network (Note 4) Max. EIRP with suitable selected PCB antenna. (Note 6) Typical output power Spurious emission l f-fsp l > 1 MHz Harmonic suppression Output capacitance (set by the automatic antenna tuning circuit) Quality factor of the output capacitance Output phase noise FSK bit rate FSK bit rate FSK frequency deviation Conditions/Notes Programmable In 433 MHz band In 868 MHz / 915 MHz bands In 433 MHz band with monopole antenna with matching network (Note 4) In 868 MHz / 915 MHz bands (Note 5) Pout Psp Pharm Co Qo Lout BRTX BRATX dffsk Selectable in 3 dB steps (Note 7) At max power 50 Ohm load (Note 4) With PCB antenna (Note 5) At max power 50 Ohm load (Note 4) With PCB antenna (Note 5) In 433 MHz band In 868 MHz / 915 MHz bands In 433 MHz band In 868 MHz / 915 MHz bands 100 kHz from carrier, in 868 MHz band 1 MHz from carrier, in 868 MHz band Via internal TX data register TX data connected to the FSK input Programmable in 15 kHz steps 15 2 2.1 13 8 2.6 2.7 15 10 -80 -103 172 256 240 kbps kbps kHz Pmax-21 Min 0.5 7 dBm 5 7 7 Pmax -55 -60 -35 -42 3.2 3.3 17 12 dBc/Hz dBm dBc dBc dBc dBc pF dBm Typ Max 6 Units mA
Pmax_ant
AC Characteristics (Turn-on/Turnaround timings)
Symbol tsx Ttx_XTAL_ON Trx_XTAL_ON Ttx_rx_SYNT_ON Trx_tx_SYNT_ON Parameter Crystal oscillator startup time Transmitter turn-on time Receiver turn-on time Transmitter - Receiver turnover time Receiver - Transmitter turnover time Conditions/Notes Default capacitance bank setting, crystal ESR < 50 Ohm (Note 9). Crystal load capacitance = 16 PF. Synthesizer off, crystal oscillator on with 10 MHz step Synthesizer off, crystal oscillator on with 10 MHz step Synthesizer and crystal oscillator on during TX/RX change with 10 MHz step Synthesizer and crystal oscillator on during RX/TX change with 10 MHz step Min Typ 2 250 250 150 150 Max 7 Units ms us us us us
AC Characteristics (Others)
Symbol Cxl tPOR tPBt Cin, D tr, f Parameter Crystal load capacitance, see crystal selection guide Internal POR timeout Wake-up timer clock accuracy Digital input capacitance Digital output rise/fall time 15 pF pure capacitive load Conditions/Notes Programmable in 0.5 pF steps, tolerance +/- 10% After Vdd has reached 90% of final value (Note 8) Crystal oscillator must be enabled to ensure proper calibration at the start up. (Note 9) +/- 10 2 10 Min 8.5 Typ Max 16 50 Units pF ms % pF ns
Notes are on page 11.
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PRELIMINARY
IA4421
AC Characteristics (continued)
Note 1: Measured with disabled clock output buffer. Note 2: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will
change accordingly.
Note 3: See the BER diagrams in the measurement results section for detailed information. Note 4: See reference design with 50 Ohm Matching Network for details. Note 5: See reference design with Resonant PCB Antenna (BIFA) for details. Note 6: Optimal antenna admittance/impedance:
IA4421 433 MHz 868 MHz 915 MHz Yantenna [mS] 2 - j5.9 1.2 - j11.9 1.49 - j12.8 Zantenna [Ohm] 52 + j152 7.8 + j83 9 + j77 Lantenna [nH] 62 15.4 13.6
Note 7: Adjustable in 8 steps. Note 8: During this period, commands are not accepted by the chip.
Note 9: The crystal oscillator start up time strongly depends on the capacitance seen by the oscillator. Low capacitance and low ESR crystal is recommended with low parasitic PCB layout design.
Note 10: By design.
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PRELIMINARY
IA4421 CONTROL INTERFACE
Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16bit command). Bits having no influence (don't care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers. The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events: * The TX register is ready to receive the next byte (RGIT) * The FIFO has received the preprogrammed amount of bits (FFIT) * Power-on reset (POR) * FIFO overflow (FFOV) / TX register underrun (RGUR) * Wake-up timer timeout (WKUP) * Negative pulse on the interrupt input pin nINT (EXT) * Supply voltage below the preprogrammed value is detected (LBD) FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the source of the IT, the status bits should be read out.
Timing Specification
Symbol tCH tCL tSS tSH tSHI tDS tDH tOD Parameter Clock high time Clock low time Select setup time (nSEL falling edge to SCK rising edge) Select hold time (SCK falling edge to nSEL rising edge) Select high time Data setup time (SDI transition to SCK rising edge) Data hold time (SCK rising edge to SDI transition) Data delay time Minimum value [ns] 25 25 10 10 25 5 5 10
Timing Diagram
tSS
nSEL
tSHI
tCH
SCK
tCL
tOD
tSH
tDS
SDI
tDH
BIT 15 BIT 14 BIT 13 BIT 8 BIT 7 BIT 1 BIT 0
SDO
FFIT
FFOV
CRL
AT S
OFFS(0)
FIFO OUT
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IA4421
Control Commands
Control Command 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Configuration Setting Command Power Management Command Frequency Setting Command Data Rate Command Receiver Control Command Data Filter Command FIFO and Reset Mode Command Synchron Pattern Command Receiver FIFO Read Command AFC Command TX Configuration Control Command PLL Setting Command Transmitter Register Write Command Wake-Up Timer Command Low Duty-Cycle Command Low Battery Detector and Microcontroller Clock Divider Command Status Read Command Related Parameters/Functions Frequency band, crystal oscillator load capacitance, RX FIFO and TX register enable Receiver/Transmitter mode change, synthesizer, crystal oscillator, PA, wake-up timer, clock output enable Frequency of the local oscillator/carrier signal Bit rate Function of pin 16, Valid Data Indicator, baseband bandwidth, LNA gain, digital RSSI threshold Data filter type, clock recovery parameters Data FIFO IT level, FIFO start control, FIFO enable and FIFO fill enable, POR sensitivity Synchron pattern RX FIFO read AFC parameters Modulation parameters, output power CLK out buffer speed, low power mode of the crystal oscillator, dithering, PLL bandwidth TX data register write Wake-up time period Enable and set low duty-cycle mode LBD voltage and microcontroller clock division ratio Status bit readout a1 to a0, rl1 to rl0, st, fi, oe, en mp, m3 to m0, p2 to p0 ob1 to ob0, ddit, ddy, bw0 t7 to t0 r4 to r0, m7 to m0 d6 to d0, en d2 to d0, v3 to v0 Related control bits el, ef, b1 to b0, x3 to x0 er, ebb, et, es, ex, eb, ew, dc f11 to f0 cs, r6 to r0 p16, d1 to d0, i2 to i0, g1 to g0, r2 to r0 al, ml, s, f2 to f0 f3 to f0, sp, ff, al, dr b7 to b0
In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the command registers after power-on.
Description of the Control Commands
1. Configuration Setting Command
Bit 15 1 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 el 6 ef 5 b1 4 b0 3 x3 2 x2 1 x1 0 x0 POR 8008h
Bit el enables the internal data register. Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.
b1 0 0 1 1 b0 0 1 0 1 Frequency Band [MHz] Reserved 433 868 915
x3 0 0 0 0 x2 0 0 0 0 x1 0 0 1 1 x0 0 1 0 1 Crystal Load Capacitance [pF] 8.5 9.0 9.5 10.0 ... 1 1 1 1 1 1 0 1 15.5 16.0
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IA4421
2. Power Management Command
Bit 15 1 14 0 13 0 12 0 11 0 10 0 9 1 8 0 7 er 6 ebb 5 et 4 es 3 ex 2 eb 1 ew 0 dc POR 8208h
Bit er ebb et es ex eb ew dc
Function of the control bit Enables the whole receiver chain The receiver baseband circuit can be separately switched on Switches on the PLL, the power amplifier, and starts the transmission (If TX register is enabled) Turns on the synthesizer Turns on the crystal oscillator Enables the low battery detector Enables the wake-up timer Disables the clock output (pin 8)
Related blocks RF front end, baseband, synthesizer, oscillator Baseband Power amplifier, synthesizer, oscillator Synthesizer Crystal oscillator Low battery detector Wake-up timer Clock output buffer
The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time. Logic connections between power control bits:
enable power amplifier
et
Edge detector
start TX
clear TX latch
(If TX latch is used)
es
enable RF synthesizer
(osc.must be on)
er
enable RF front end
enable baseband circuits ebb
(synt. must be on)
enable oscillator ex
Note: * If both et and er bits are set the chip goes to receive mode. * FSK / nFFSEL input are equipped with internal pull-up resistor. To achieve minimum current consumption do not pull this input to logic low in sleep mode.
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IA4421
3. Frequency Setting Command
Bit
15 1
14 0
13 1
12 0
11 f11
10 f10
9 f9
8 f8
7 f7
6 f6
5 f5
4 f4
3 f3
2 f2
1 f1
0 f0
POR A680h
The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F value sent is out of range, the previous value is kept. The synthesizer center frequency f0 can be calculated as: f0 = 10 * C1 * (C2 + F/4000) [MHz]
The constants C1 and C2 are determined by the selected band as:
Band [MHz] 433 868 915 C1 1 2 3 C2 43 43 30
4. Data Rate Command
Bit
15 1 14 1 13 0 12 0 11 0 10 1 9 1 8 0 7 cs 6 r6 5 r5 4 r4 3 r3 2 r2 1 r1 0 r0 POR C623h
The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit parameter R (bits r6 to r0) and bit cs. BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps] In the receiver set R according to the next function: R= (10000 / 29 / (1+cs*7) / BR) - 1, where BR is the expected bit rate in kbps. Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error. Data rate accuracy requirements: Clock recovery in slow mode: BR/BR < 1/(29*Nbit) Clock recovery in fast mode: BR/BR < 3/(29*Nbit) BR is the bit rate set in the receiver and BR is the bit rate difference between the transmitter and the receiver. Nbit is the maximum number of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and to be careful to use the same division ratio in the receiver and in the transmitter. 5. Receiver Control Command
Bit 15 1 14 0 13 0 12 1 11 0 10 p16 9 d1 8 d0 7 i2 6 i1 5 i0 4 g1 3 g0 2 r2 1 r1 0 r0 POR 9080h
Bit 10 (p16): pin16 function select
p16 0 1 Function of pin 16 Interrupt input VDI output
Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:
d1 0 0 1 1 d0 0 1 0 1 Response Fast Medium Slow Always on
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IA4421
DQD CR_LOCK
MUX d0 d1 FAST SEL0 SEL1 IN0 IN1 IN2 IN3 CLR Y VDI
DRSSI DQD
MEDIUM SLOW LOGIC HIGH
DRSSI DQD CR_LOCK
SET
Q
er *
R/S FF
CLR
Note: * For details see the Power Management Command
Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:
i2 0 0 0 0 1 1 1 1 i1 0 0 1 1 0 0 1 1 i0 0 1 0 1 0 1 0 1 BW [kHz] reserved 400 340 270 200 134 67 reserved
Bits 4-3 (g1 to g0): LNA gain select:
g1 0 0 1 1 g0 0 1 0 1 relative to maximum [dB] 0 -6 -14 -20
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IA4421
Bits 2-0 (r2 to r0): RSSI detector threshold:
r2 0 0 0 0 1 1 1 1 r1 0 0 1 1 0 0 1 1 r0 0 1 0 1 0 1 0 1 RSSIsetth [dBm] -103 -97 -91 -85 -79 -73 Reserved Reserved
The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: RSSIth=RSSIsetth+GLNA
6. Data Filter Command
Bit 15 1
14 1
13 0
12 0
11 0
10 0
9 1
8 0
7 al
6 ml
5 1
4 s
3 1
2 f2
1 f1
0 f0
POR C22Ch
Bit 7 (al): Clock recovery (CR) auto lock control, if set. CR will start in fast mode, then after locking it will automatically switch to slow mode. Bit 6 (ml): Clock recovery lock control 1: fast mode, fast attack and fast release (4 to 8 bit preamble (1010...) is recommended) 0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended) Using the slow mode requires more accurate bit timing (see Data Rate Command). Bits 4 (s): Select the type of the data filter:
s 0 1 Filter Type Digital filter Analog RC filter
Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically adjusted to the bit rate defined by the Data Rate Command. Note: Bit rate can not exceed 115 kpbs in this mode. Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external capacitor connected to this pin and VSS. The table shows the optimal filter capacitor values for different data rates
1.2 kbps 12 nF 2.4 kbps 8.2 nF 4.8 kbps 6.8 nF 9.6 kbps 3.3 nF 19.2 kbps 1.5 nF 38.4 kbps 680 pF 57.6 kbps 270 pF 115.2 kbps 150 pF 256 kbps 100 pF
Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used. Bits 2-0 (f2 to f0): DQD threshold parameter.
Note: To let the DQD report "good signal quality" the threshold parameter should be 4 in cases where the bitrate is close to the deviation. At higher deviation/bitrate settings, a higher threshold parameter can report "good signal quality" as well.
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7. FIFO and Reset Mode Command
Bit 15 1 14 1 13 0 12 0 11 1 10 0 9 1 8 0 7 f3 6 f2 5 f1 4 f0 3 sp 2 al 1 ff 0 dr POR CA80h
Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level. Bit 3 (sp): Select the length of the synchron pattern:
sp 0 1 Byte1 2Dh Not used Byte0 (POR) D4h D4h Synchron Pattern (Byte1+Byte0) 2DD4h D4h
Note: Byte0 can be programmed by the Synchron Pattern Command. Bit 2 (al): Set the input of the FIFO fill start condition:
al 0 1
Synchron pattern Always fill
FIFO_Logic (simplified)
Synchron Pattern Detector
al*
Latch FIFO_WRITE _EN
FIFO_IT .....
FIFO_OVERFL CR_LOCK DQD
EN
FIFO_OVERFL
nRES
ff* ef** er***
nFIFO_RESET
PIN 6 I/O port
ef**
DIRECTION
Note: For details see the * Output and FIFO mode Command, ** Configuration Setting Command, *** Power Management Command
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared. Bit 0 (dr): Disables the highly sensitive RESET mode.
Reset mode Sensitive reset dr=0 Non-sensitive reset dr=1 Reset triggered when Vdd below 1.5V Vdd glitch greater than 500mV Vdd below 0.25V
Note: To restart the synchron pattern recognition, bit 1 should be cleared and set.
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IA4421
8. Synchron Pattern Command
Bit 15 1 14 1 13 0 12 0 11 1 10 1 9 1 8 0 7 b7 6 b6 5 b5 4 b4 3 b3 2 b2 1 b1 0 b0 POR CED4h
The Byte0 used for synchron pattern detection can be reprogrammed by B . 9. Receiver FIFO Read Command
Bit 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POR B000h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
Note:: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the clock
signal is not 50 % the shorter period of the clock pulse width should be at least 2/fref .
10. AFC Command
Bit 15 1
14 1
13 0
12 0
11 0
10 1
9 0
8 0
7 a1
6 a0
5 rl1
4 rl0
3 st
2 fi
1 oe
0 en
POR C4F7h
Bit 7-6 (a1 to a0): Automatic operation mode selector:
a1 0 0 1 1 a0 0 1 0 1 Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the foffset only during receiving (VDI=high) Keep the foffset value independently from the state of the VDI signal
Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
rl1 0 0 1 1 rl0 0 1 0 1 Max deviation No restriction +15 fres to -16 fres +7 fres to -8 fres +3 fres to -4 fres
fres: 433 MHz bands: 2.5 kHz 868 MHz band: 5 kHz 915 MHz band: 7.5 kHz
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IA4421
Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block.
Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice as long, but the measurement uncertainty is about half.
Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL. Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.
BASEBAND SIGNAL IN
ATGL** ASAME***
fi 10MHz CLK
FINE
SE L Y I0
CLK
DIGITAL LIMITER DIGITAL AFC 7 CORE LOGIC
IF IN>MaxDEV THEN OUT=MaxDEV
7 BIT
FREQ. OFFSET REGISTER
OFFS <6:0>
12 BIT ADDER Fcorr<11:0> Corrected frequency parameter to synthesizer
/4 en VDI* a1 to a0 Power-on reset (POR) rl1 to rl0 st oe F<11:0> Parameter from Frequency control word
I1 MUX
7
ENABLE CALCULATION
AUTO OPERATION
singals for auto operation modes
IF INCLK CLR
RANGE LIMIT strobe STROBE output enable OUTPUT ENABLE
NOTE: * VDI (valid data indicator) is an internal signal of the controller. See the Receiver Setting Command for details. ** ATGL: toggling in each measurement cycle *** ASAME: logic high when the result is stable
Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring results are the same, toggle bit changes state in every measurement cycle.
In manual mode, the strobe signal is provided by the microcontroller. One measurement cycle (and strobe) signal can compensate about 50-60% of the actual frequency offset. Two measurement cycles can compensate 80%, and three measurement cycles can compensate 92%. The ATGL bit in the status register can be used to determine when the actual measurement cycle is finished. In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the same result in two subsequent cycles.
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There are three operation modes, examples from the possible application: 1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, extended TX-RX maximum distance can be achieved. Possible application: In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an interferer. 2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern -easier to receive- (i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the corrected frequency settings. 2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility of reducing it. In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use these settings when receiving signals from different transmitters transmitting in the same nominal frequencies. 3, (a1=1, a0=1) It's the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a complete measuring cycle, the measured value is kept independently of the state of the VDI signal. 11. TX Configuration Control Command
Bit 15 1 14 0 13 0 12 1 11 1 10 0 9 0 8 mp 7 m3 6 m2 5 m1 4 m0 3 0 2 p2 1 p1 0 p0 POR 9800h
Bits 8-4 (mp, m3 to m0): FSK modulation parameters:
The resulting output frequency can be calculated as: fout = f0 + (-1)SIGN * (M + 1) * (15 kHz) where: f0 is the channel center frequency (see the Frequency Setting Command) M is the four bit binary number SIGN = (mp) XOR FSK Bits 2-0 (p2 to p0): Output power:
p2 0 0 0 0 1 1 1 1 p1 0 0 1 1 0 0 1 1 p0 0 1 0 1 0 1 0 1 Relative Output Power [dB] 0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5
mp=0 and FSK=0 or mp=1 and FSK=1
P out df fsk df fsk
f0
f out
mp=0 and FSK=1 or mp=1 and FSK=0
Note:
* FSK represents the value of the actual data bit.
*
The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance. (See: Antenna Application Note: IA ISM-AN1)
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12. PLL Setting Command
Bit 15 1 14 1 13 0 12 0 11 1 10 1 9 0 8 0 7 0 6 ob1 5 ob0 4 1 3 ddy 2 ddit 1 1 0 bw0 POR CC67h
Note: POR default setting of the register carefully selected to cover almost all typical applications.
Bit 6-5 (ob1-ob0): Microcontroller output clock buffer rise and fall time control.
ob1 0 0 1 ob0 0 1 X Selected uC CLK frequency 5 or 10 MHz (recommended) 3.3 MHz 2.5 MHz or less
Note: Needed for optimization of the RF performance. Optimal settings can vary according to the external load capacitance. (Typ conditions: Top = 27 oC; Vdd = Voc = 2.7 V, Crystal ESR = 30 Ohm) Bit 3 (ddy): Bit 2 (ddit): Bit 0 (bw0):
bw0 0 1
Switches on the delay in the phase detector when this bit is set. When set, disables the dithering in the PLL loop. PLL bandwidth can be set for optimal TX RF performance.
Max bit rate [kbps] 86.2 256 Phase noise at 1MHz offset [dBc/Hz] -107 -102
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13. Transmitter Register Write Command
Bit 15 1 14 0 13 1 12 1 11 1 10 0 9 0 8 0 7 t7 6 t6 5 t5 4 t4 3 t3 2 t2 1 t1 0 t0 POR B8AAh
With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting Command. Multiple Byte Write with Transmit Register Write Command:
Note: Alternately the transmit register can be directly accessed by nFFSEL (pin6). 14. Wake-Up Timer Command
Bit 15 1 14 1 13 1 12 r4 11 r3 10 r2 9 r1 8 r0 7 m7 6 m6 5 m5 4 m4 3 m3 2 m2 1 m1 0 m0 POR E196h
The wake-up time period can be calculated by (m7 to m0) and (r4 to r0): Twake-up = 1.03 * M * 2R + 0.5 [ms] Note: * For continual operation the ew bit should be cleared and set at the end of every cycle. * For future compatibility, use R in a range of 0 and 29. 15. Low Duty-Cycle Command
Bit 15 1
14 1
13 0
12 0
11 1
10 0
9 0
8 0
7 d6
6 d5
5 d4
4 d3
3 d2
2 d1
1 d0
0 en
POR C80Eh
With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode. The time cycle is determined by the Wake-Up Timer Command. The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.) Duty-Cycle= (D * 2 +1) / M *100% The on-cycle is automatically extended while DQD indicates good received signal condition (FSK transmission is detected in the frequency range determined by Frequency Setting Command plus and minus the baseband filter bandwidth determined by the Receiver Control Command).
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IA4421
Application Proposal For LPDM (Low Power Duty-Cycle Mode) Receivers:
Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt is not generated in this mode. Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command. 16. Low Battery Detector and Microcontroller Clock Divider Command
Bit 15 1
14 1
13 0
12 0
11 0
10 0
9 0
8 0
7 d2
6 d1
5 d0
4 0
3 v3
2 v2
1 v1
0 v0
POR C000h
The 4 bit parameter (v3 to v0) represents the value V, which defines the threshold voltage Vlb of the detector: Vlb= 2.25 + V * 0.1 [V]
Clock divider configuration:
d2 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 Clock Output Frequency [MHz] 1 1.25 1.66 2 2.5 3.33 5 10
The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command.
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IA4421
17. Status Read Command The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits will be clocked out on the SDO pin as follows: Status Register Read Sequence with FIFO Read Example:
RGIT FFIT POR RGUR FFOV WKUP EXT LBD FFEM ATS RSSI DQD CRL ATGL OFFS(6) OFFS(3) -OFFS(0)
TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command) The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the FIFO read methods) Power-on reset (Cleared after Status Read Command) TX register under run, register over write (Cleared after Status Read Command) RX FIFO overflow (Cleared after Status Read Command) Wake-up timer overflow (Cleared after Status Read Command) Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command) Low battery detect, the power supply voltage is below the pre-programmed limit FIFO is empty Antenna tuning circuit detected strong enough RF signal The strength of the incoming signal is above the pre-programmed limit Data quality detector output Clock recovery locked Toggling in each AFC cycle MSB of the measured frequency offset (sign of the offset value) Offset value to be added to the value of the frequency control parameter (Four LSB bits)
Note: In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).
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IA4421 TX REGISTER BUFFERED DATA TRANSMISSION
In this operating mode (enabled by bit el, in the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller. TX register simplified block diagram (before transmit)
TX register simplified block diagram (during transmit)
Typical TX register usage
Note: The content of the data registers are initialized by clearing bit et.
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PRELIMINARY
IA4421 RX FIFO BUFFERED DATA READ
In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller. Interrupt Controlled Mode: The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case. Polling Mode: When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be clocked out by the SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be taken. An SPI read command is also available to read out the content of the FIFO. FIFO Read Example with FFIT Polling
nSEL 0 SCK 1 2 3 4
nFFS FIFO read out SDO
FIFO OUT FO+1 FO+2 FO+3 FO+4
FFIT
Note:: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the clock signal is not 50 % the shorter period of the clock pulse should be at least 2/fref .
RECOMMENDED PACKET STRUCTURES
Preamble Minimum length Recommended length 4 - 8 bit (1010b or 0101b) 8 -12 bit (e.g. AAh or 55h) Synchron word (Can be network ID) D4h (programmable) 2DD4h (D4 is programmable) Payload ? ? CRC 4 bit - 1 byte 2 byte
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IA4421 CRYSTAL SELECTION GUIDELINES
The crystal oscillator of the IA4421 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used. When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup. The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO). Therefore fLO is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error. Whenever a low frequency error is essential for the application, it is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the "midrange", for example 16 pF. The "pull-ability" of the crystal is defined by its motional capacitance and C0.
Maximum XTAL Tolerances Including Temperature and Aging [ppm]
Bit Rate: 2.4 kbps 30 433 MHz 868 MHz 915 MHz 20 10 10 45 30 20 15 60 50 25 25 Deviation [+/- kHz] 75 70 30 30 90 90 40 40 105 100 50 50 120 100 60 50
Bit Rate: 9.6 kbps 30 433 MHz 868 MHz 915 MHz 15 8 8 45 30 15 15 60 50 25 25
Deviation [+/- kHz] 75 70 30 30 90 80 40 40 105 100 50 50 120 100 60 50
Bit Rate: 38.4 kbps 30 433 MHz 868 MHz 915 MHz don't use don't use don't use 45 5 3 3 60 20 10 10
Deviation [+/- kHz] 75 30 20 15 90 50 25 25 105 75 30 30 120 75 40 40
Bit Rate: 115.2 kbps 105 433 MHz 868 MHz 915 MHz don't use don't use don't use 120 3 don't use don't use 135 20 10 10
Deviation [+/- kHz] 150 30 20 15 165 50 25 25 180 70 35 30 195 80 45 40
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IA4421 RX-TX ALIGNMENT PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs. To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have identical frequencies. It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).
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IA4421 TYPICAL PERFORMANCE CHARACTERISTICS
Channel Selectivity and Blocking:
90 80 70 60 50 dB 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 11 12 CW interferer offset from carrier [MHz] 434 MHz 868 MHz ETSI
Note: * LNA gain maximum, filter bandwidth 67 kHz, data rate 9.6 kbps, AFC switched off, FSK deviation +/- 45 kHz, Vdd = 2.7 V * Measured according to the descriptions in the ETSI Standard EN 300 220-1 v2.1.1 (2006-01 Final Draft), section 9 * The ETSI limit given in the figure is drawn by taking 109dBm typical sensitivity into account, and corresponds to receiver class 2 requirements (section 4.1.1)
Phase Noise Performance in the 433, 868 and 915 MHz Bands:
433 MHz 868 MHz 915 MHz
(Measured under typical conditions: Top = 27 oC; Vdd = Voc = 2.7 V)
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IA4421
BER Curves in 433 MHz Band:
Sensitivity at 434 MHz 1.E+00 -120 1.E-01 1.E-02 BER 1.E-03 1.E-04 1.E-05 1.E-06 Input power [dBm]
-115
-110
-105
-100
-95
-90 1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k
BER Curves in 868 MHz Band:
Sensitivity at 868 MHz 1.E+00 -115 1.E-01 1.E-02 BER 1.E-03 1.E-04 1.E-05 1.E-06 Input power [dBm]
-110
-105
-100
-95
-90
-85
1.2k 2.4k 4.8k 9.6k 19.2k 38.4k 57.6k 115.2k
The table below shows the optimal receiver baseband bandwidth (BW) and transmitter deviation frequency (dFfsk) settings for different data-rates supposing no transmit receive offset frequency. If TX/RX offset (for example due to Xtal tolerances) have to be taken into account, increase the BW accordingly.
1.2 kbps BW=67 kHz fFSK =45 kHz 2.4 kbps BW=67 kHz fFSK =45 kHz 4.8 kbps BW=67 kHz fFSK =45kHz 9.6 kbps BW=67 kHz fFSK =45 kHz 19.2 kbps BW=67 kHz fFSK =45 kHz 38.4 kbps BW=134 kHz fFSK =90 kHz 57.6 kbps BW=134 kHz fFSK =90 kHz 115.2 kbps BW=200 kHz fFSK =120 kHz
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IA4421
Receiver Sensitivity over Ambient Temperature (433 MHz, 9.6 kbps, fFSK: 45 kHz, BW: 67 kHz):
434 MHz -100
-103
-106 dBm
2.2V 2.7V 3.3V 3.8V
-109
-112
-115 -50 -25 0 25 Celsius 50 75 100
Receiver Sensitivity over Ambient Temperature (868 MHz, 9.6 kbps, fFSK: 45 kHz, BW: 67 kHz):
868 MHz -100
-103
-106 dBm
2.2V 2.7V 3.3V 3.8V
-109
-112
-115 -50 -25 0 25 Celsius 50 75 100
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IA4421 REFERENCE DESIGNS
50 Ohm Matching Network
Schematics
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IA4421
PCB Layout
Top View
Bottom View
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IA4421
Resonant PCB Antenna (BIFA)
Schematics
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IA4421
PCB Layout (Antenna designed for 870 MHz band)
Top View
Bottom View
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IA4421
Package Information
16-pin TSSOP
See Detail "A"
Section B-B
Gauge Plane 0.25
Detail "A"
Symbol A A1 A2 b b1 c c1 D e E E1 L L1 R R1 1 2 3
Min. 0, 05 0,80 0, 19 0,19 0, 09 0, 09 4,90
4,30 0,50 0, 09 0, 09 0
Dimensions in mm Nom. Max. 1, 20 0, 15 0,90 1,05 0, 30 0,22 0,25 0, 20 0, 16 5,00 5,10 0.65 BSC. 6.40 BSC. 4,40 4,50 0,60 0,75 1.00 REF.
8 12 REF. 12 REF.
Dimensions in Inches Nom. Max. 0,047 0, 002 0, 006 0,031 0,035 0,041 0, 007 0, 012 0,007 0,009 0,010 0, 004 0, 008 0, 004 0, 006 0,193 0,197 0,201 0.026 BSC. 0.252 BSC. 0,169 0,173 0,177 0,020 0,024 0,030 0.39 REF. 0, 004 0,004 0 8 12 REF. 12 REF. Min.
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IA4421 RELATED PRODUCTS AND DOCUMENTS
IA4421 Universal ISM Band FSK Transceiver
DESCRIPTION IA4421 16-pin TSSOP ORDERING NUMBER IA4421-IC CC16 Revision #
Demo Boards and Development Kits
DESCRIPTION Development Kit ISM Repeater Demo ORDERING NUMBER IA ISM - DK IA ISM - DARP
Related Resources
DESCRIPTION Antenna Selection Guide Antenna Development Guide IA4221 Universal ISM Band FSK Transmitter IA4320 Universal ISM Band FSK Receiver ORDERING NUMBER IA ISM - AN1 IA ISM - AN2 See www.integration.com for details See www.integration.com for details
Note: Volume orders must include chip revision to be accepted.
Integration Associates, Inc. 110 Pioneer Way, Unit L Mountain View, California 94041 Tel: 650.969.4100 Fax: 650.969.4582 www.integration.com marketing@integration.com wireless.support@integration.com P707
This document may contain preliminary information and is subject to change by Integration Associates, Inc. without notice. Integration Associates assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Integration Associates or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
(c)2007 Integration Associates, Inc. All rights reserved. Integration Associates is a trademark of Integration Associates, Inc. All other trademarks belong to their respective owners.
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